In digital systems, it is frequently necessary to interface different parts of the system which handle data at different rates. For example, it is often desirable to interface a disk drive to a central processing unit (CPU). Commonly, a first-in, first-out (FIFO) memory is used to perform this interface. A FIFO memory is a storage device that allows data to be written into it and read from it at different data rates.
Certain recent FIFO memories have the capability to store sixteen words, and use a write pointer to latch a current write address. While the write occurs to a memory location in the memory, the write pointer increments to the next location. This architecture, called a simultaneous memory write architecture, allows for a shorter write cycle time. An example of such a FIFO memory is described in our co-pending application Ser. No. 892,228, filed Aug. 1, 1986. Now U.S. Pat. No. 4,829,475. This memory employs a write address ring counter and a read address ring counter. The write address ring counter sequentially addresses each memory word location in response to input write commands. The read address ring counter operates similarly to sequentially read memory word locations responsive to input read commands. A comparator is provided for this device for comparing the current address of the write address ring counter with that of the read address ring counter. When equality exists between the counters, and if the last memory operation was a read operation, the next read operation will be inhibited by an EMPTY flag. On the other hand, if the write and read address ring counters point to the same memory location, and the last operation was a write operation, a further write operation without an intervening read will be inhibited by a FULL flag.
More recently, there has been a demand in the industry for one-chip FIFO memories with more capacity, such as a 64-word size. In addition, the industry has begun to specify that the FIFO memory outputs include, in addition to the EMPTY and FULL flags already mentioned, an ALMOST-FULL/ALMOST-EMPTY flag and a HALF-FULL flag.
Several schemes have been developed in order to select which of the words in a 64-word FIFO will be written into or read out of. One such scheme is to employ an n stage ring counter, where n is the number of memory words. The n ring counter method requires 64 flip-flops but no decoding circuitry. Another scheme is the log.sub.2 n stage binary counter. This scheme requires six flip-flops, but also requires 64 6-input AND gates for decoding purposes.
Certain recent FIFO memories use a monostable multivibrator or one-shot generator in order to originate a WRITE CLOCK pulse for actuating the write address ring counter. As will be described in more detail below, one conventional approach is to input a non-delayed input signal into a NAND gate, and to also input the signal into a delay path including an RC circuit. The delay path inverts the delayed signal at its output, which is connected as an input to the NAND gate. Therefore, this one-shot generator will produce a signal as long as the inverted, delayed input has yet to be received by the NAND gate.
The dependence of this one-shot generator on an RC time constant causes problems in regulating the width of the one-shot output pulse. This output pulse must be wide enough for the pointers to successfully increment to a new location and to complete a memory write, but not so wide that the maximum clocking rate suffers. This one-shot circuit also produces a pulse width that is variable with the voltage swing of the signal. Both the RC delay and the voltage swing can substantially vary due to processing variations.
Conventional FIFO memories have a plurality of cell locations that are continuously powered up and enabled for either a memory write operation or a memory read operation. Where TTL logic is used, this requires a large amount of power consumption.
From the above, it can be seen that a need has arisen in the industry for a FIFO memory that: (a) has a larger-than-sixteen-word capacity, but is not unduly complex in its pointer and decoder circuitry; (b) is capable of generating FULL, EMPTY, ALMOST-FULL/ALMOST-EMPTY, and HALF-FULL flags with a minimum of extra circuitry; (c) incorporates a monostable multivibrator or one-shot generator with a more precisely controlled pulse width; and (d) has a memory cell design with decreased power consumption.